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12 january 98 42 1714 01 the information in this datasheet is subject to change 1/66 ST18952 digital signal processor (dsp) chip preliminary data n programmable d950 core n data calculation unit n address calculation unit n program control unit n fast and flexible buses n 66mips - 15 ns instruction cycle time n 16.5 kwords data memory (ram) n 32 kwords program memory (ra42 1714 01) n interrupt controller n dma controller n serial input/output n timer n bus switch unit n emulation unit n jtag ieee 1149.1 test access port tap emulation unit 2 timers 2 serial i/o interrupt controller 16.5 kwords data memory bus switch unit dma controller d950 core 32 kwords program memory
2/66 table of contents 3 1 introduction . . . . . . . . .................................................. 4 2 pin description . . . . . .................................................. 5 3 functional overview . . . . . . . . . . . . . . . . . . ................................. 9 4 d950core .......................................................... 12 4.1 d950core registers . . . . . . . . ....................................... 14 5 memory ............................................................ 15 5.1 internal memory resource . . . ....................................... 15 5.2 direct bus extension . . . . . . . . . . . . . . . . . . . . . . . . . ..................... 16 6 bus switch unit . . . . . . . . . . . . . . . . . . . . . . . . . ............................. 18 6.1 bsuoperation ................................................... 18 6.2 bsu control registers . . . . . . . ....................................... 19 7 dma controller . . . . . ................................................. 21 7.1 dma operation . . . . ............................................... 22 7.2 dma registers . . . . . . . ............................................ 23 8 interrupt controller . . . . . ............................................... 26 8.1 interrupt controller registers . . . . . . . . ................................. 27 9 timers ............................................................. 31 9.1 timerregisters ................................................... 31 10 sio ............................................................... 35 10.1 sio registers . . . . . . . . . . . . . . . . . ................................... 35 11 external coprocessor . . . . . ............................................ 41 12 systemcontrol ...................................................... 41 12.1 system registers ................................................. 42 12.2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .......................... 44 13 jtag ieee 1149.1 test access port ...................................... 45 14 emulation unit . . . . . . ................................................. 45 15 electrical specifications ................................................ 47 15.1 dc absolute maximum ratings ...................................... 47 15.2 dc electrical characteristics . . . . . . . . . . . . . . . . ........................ 47 15.3 ac characteristics . . . ............................................. 48 16 y space memory mapping . . . . . ....................................... 56 16.1 memorymap .................................................... 56 16.2 serial input/output registers . . . . . . . . . . . . . . . . . ........................ 56 16.3 timerregisters ................................................... 58 16.4 bus switch unit registers . . . . . . . . . . ................................. 58 1
3/66 table of contents 16.5 system control registers . . . . . . . . . . ................................. 58 16.6 dma controller registers . . . . . . . . . . . . . .............................. 59 16.7 interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............. 59 16.8 emulation unit registers . . . . . . . . . . . . . . .............................. 60 16.9 d950core control registers . . . . . . . . . . . . . . . . . . . . . . . .................. 60 17 ST18952 package specifications . ....................................... 61 17.1 208 pin pqfp pinout . . . . . . . . . . .................................... 61 17.2 208 pin pqfp package dimensions . . . . . ............................. 62 18 deviceid ........................................................... 64 19 ordering information . . . . . . . . . . . . ...................................... 64 20 revision history . . . . . . . ............................................... 64
4/66 ST18952 1 introduction the ST18952 chip includes the sgs-thomson d950 16-bit fixed point digital signal processor core, 16.5 kwords of data memory, 32 kwords of program memory, and the following on-chip peripherals: ? interrupt controller (itc) ? dma controller (dma) ? bus switch unit (bsu) ? synchronous input/output (sio) ? timer (tim) ? emulation unit (emu) ? tap controller (tap) it also includes an oscillator and a pll for generation of the d950core clock. the ST18952 is used on the d950 emulation card (called the d952 module) developed by sgs-thomson. it can also be used for application development by customers. custom development is eased by providing direct access to the d950 instruction and data buses to allow simultaneous access to external memories or peripherals (with wait-states). for full details of the d950core refer to the d950core datasheet ( document number 42-1709 ). 2
5/66 ST18952 2 pin description the following tables detail the ST18952 pin set. there is one table for each group of pins. the tables detail the pin name, type and a short description of the pin function. signal names have an overbar if they are active low, otherwise they are active high. table 2.1 direct i bus extension (35 pins) table 2.2 direct y bus extension (35 pins) table 2.3 direct x bus extension / bus extension through bus switch unit (39 pins) pin name type description ide0-15 i/o instruction data extension bus. iae0-15 o instruction address extension bus. irde o i-extension bus read strobe. active low. iwre o i-extension bus write strobe. active low. ibse o i-extension bus strobe. active low. pin name type description yde0-15 i/o y data extension bus. yae0-15 o y address extension bus. yrde o y-extension bus read strobe. active low. ywre o y-extension bus write strobe. active low. ybse o y-extension bus strobe. active low. pin name type description ed_xde0-15 i/o multiplexed input/output. bus switch unit extension data bus or x data exten- sion bus. ea_xae0-15 o multiplexed output. bus switch unit extension address bus or x address ex- tension bus. eird o bsu eird output eiwr o bsu eiwr output xbse o x extension bus data strobe eyrd o bsu eyrd output eywr o bsu eywr output xrde_exrd o multiplexed output. x-extension bus read strobe (xrde) or bsu exrd output. xwre_exwr o multiplexed output. x-extension bus write strobe (xwre) or bsu exwr output.
6/66 ST18952 table 2.4 general purpose parallel port / interrupt requests (8 pins) table 2.5 clocks (6 pins) table 2.6 bus control (3 pins) pin name type description p_itrq0-7 i/o multiplexed input/output. parallel port i/o or external interrupt request (itrq). pin name type description extal i oscillator input. xtal o oscillator output. nominal oscillator frequency is 27 mhz. mclk i master clock input (use of external clock generator). clk_mode i clock mode select input. when low the oscillator and internal pll are enabled. the 950 receives its master clock from the pll at 5 times the oscillator frequency. when high the pll is disabled. the d950 receives its master clock from mclk. incycle o instruction cycle. asserted high for 1 clkout cycle at the beginning of instruction cycle. clkout o output clock (at input clock/2 frequency). pin name type description dtack i data transfer acknowledge input. active low. it is combined in a or gate with bsu dtack output in order to generate the dtack signal for the d950core. it controls extension of bus cycles by inser- tion of wait-states when using external memory either through bus-switch or direct extension. hold i external bus hold request input. active low. holdack o hold acknowledge output. active low.
7/66 ST18952 table 2.7 d950core control (10 pins) table 2.8 emulation unit (7 pins) pin name type description reset i reset input. active low. initializes the 950-core to the reset state. reset_out o reset output (system reset). active low. lp i low power input. active low. lpack o low power acknowledge. active low. mode i mode selection for reset. 0: forces reset address to 0x0000 1: forces reset address to 0xfc00 ird_wr o program memory read/write indicator. vci o valid coprocessor instruction output. asserted low during the instruction cycle preceding a coprocessor instruc- tion to enable operation of an external coprocessor. stackx o x stack read/write instruction flag. stacky o y stack read/write instruction flag. idt_en i i-bus direct transfer enable (to bsu peripheral). active low. pin name type description erq i emulator halt request. active low. halts program execution and enters emulation mode. idle o output flag asserted high when the processor is halted due to an emulation halt request or a valid breakpoint condition.asserted low when the proces- sor is not halted or during execution of an instruction under control of the emulator. haltack o halt acknowledge. active high. asserted high when the processor is halted from an emulator halt request or when a valid breakpoint condition is met. snap o snapshot. active high. asserted high when executing an instruction if snapshot mode is enabled. axebp i enable breakpoint on x address bus when high. ayebp i enable breakpoint on y address bus when high. aiebp_scan_en i enable breakpoint on i address bus when high.
8/66 ST18952 table 2.9 jtag ieee 1149.1 test access port (5 pins) table 2.10 dma controller / serial input/output (8 pins) pin name type description tdi i test data input. tck i test clock. tms i test mode select. tdo o test data output. trst i test logic reset (also used for emulator module). active low. pin name type description dmarq0/srd0 i dma request 0 or sio0 receive data dmarq1/sck0 i/o dma request 1 or sio0 data clock dmarq2/srd1 i dma request 2 or sio1 receive data dmarq3/sck1 i/o dma request 3 or sio1 data clock dmack0/std0 o dma acknowledge 0 or sio0 transmit data dmack1/sfs0 i/o dma acknowledge 1 or sio0 frame synchronizer dmack2/std1 o dma acknowledge 2 or sio1 transmit data dmack3/sfs1 i/o dma acknowledge 3 or sio1 frame synchronizer
9/66 ST18952 3 functional overview a block diagram of the ST18952 is shown below. the modules that comprise the ST18952 are outlined in this section and described in detail in the following sections. figure 3.1 ST18952 block diagram y x d950core dma tap interrupt 8k x 16 bus 8k x 16 8k x 16 i osc + pll x/y 0.5k x 16 emulation control i/os/ port jtag port (x 4) output clocks input clock + control timer 0 sio 1 timer 1 sio 0 controller switch unit unit controller direct extension buses ext. bus
10/66 ST18952 d950core the d950core is a general purpose programmable 16-bit fixed point digital signal processor core. the main blocks of the d950core include an arithmetic data calculation unit, a program control unit and an address calculation unit, able to manage up to 64k (program) and 128k (data) x 16-bit memory spaces. memory one 32 kword and two 8 kword single port memories are included on-chip: ? 32 kword instruction memory on i space ? 8 kword x-data memory on x space ? 8 kword y-data memory on y space one 512 word dual port memory is shared on x and y spaces. memory can be extended off-chip for all three spaces in two ways: 1: directly - accesses to program and data memories can be performed simulta- neously. insertion of wait-states is necessary in case of nominal frequency work. 2: through the bus switch unit - accesses to the different external spaces are mul- tiplexed and wait-states are added. bus switch unit the bus switch unit (bsu) is a bi-directional switcher which switches the 3 internal buses (i, x and y) to the external (e) bus. dma controller the dma controller manages data transfer between memories and external peripherals. there are four independent dma channels. transfers can occur on x/y/i spaces (simultaneous transfers on x and y spaces). interrupt controller the interrupt controller (itc) can manage up to eight external interrupts. each source can be individually activated and programmed as edge or level triggered. a `pending interrupt' flag displays the source waiting for service (this flag is writable to allow a software interrupt capability). the priority of interrupts is programmable. timers there are two timer (tim) units on the ST18952. the timers enable interrupts to be generated after predefined periods of time.
11/66 ST18952 sio there are two synchronous serial input/output (sio) ports enable a link to serial devices such as codecs and to other processors. oscillator and pll a 27 mhz crystal can be used with the on-chip oscillator and pll to provide the d950core clock input. the pll module multiplies the oscillator frequency by a factor of 10 and generates a 270 mhz signal. a programmable divider is connected to the pll output to generate the d950 clock input. the division range is 2 to 256. emulation unit and jtag ieee 1149.1 test access port the emulation unit (emu) performs functions dedicated to emulation and test through the external ieee 1149.1 jtag interface.
12/66 ST18952 4 d950core the d950core is composed of three main units. ? data calculation unit (dcu) ? address calculation unit (acu) ? program control unit (pcu) for full details of the d950 dsp core refer to the d950core datasheet ( document number 42- 1709 ). these units are organized in an harvard architecture around three bidirectional 16-bit buses, two for data and one for instruction. each of these buses is dedicated to an uni- directional 16-bit address bus (xa/ya/ia). an 8-bit general purpose parallel port (p0-p7) can be configured (input or output). a test condition is attached to each bit to test external events. the d950core is controlled through interface pins related to interrupt, low-power mode, reset and miscellaneous functions. figure 4.1 d950core block diagram data calculation unit address calculation unit program control unit clkin data memory program memory vdd vss test & emulation po/p7 control 11 8 14 xd-bus yd-bus 6 16 16 16 16 3 16 16 output clocks xa-bus ya-bus id-bus ia-bus control
13/66 ST18952 data buses (xd/yd and xa/ya) are provided externally. data memories (ram, rom) and peripherals registers are mapped in these address spaces. instruction bus (id/ia) gives access to program memory (ram, rom). each bus has its own control interface. table 4.1 data/instruction bus and corresponding address bus. depending on the calculation mode, the d950core dcu computes operands which can be considered as 16 or 32-bit, signed or unsigned. it includes a 16 x 16-bit parallel multiplier able to implement mac-based functions in one cycle per mac. a 40-bit arithmetic and logic unit, including an 8-bit extension for arithmetic operations, implements a wide range of arithmetic and logic functions. a 40-bit barrel shifter unit and a bit manipulation unit are included. the tables below illustrate the different types of word length and word format available for manipulation. table 4.2 summary of possible word lengths and formats data/instruction bus corresponding address bus xd bidirectional 16-bit xa unidirectional 16-bit yd bidirectional 16-bit ya unidirectional 16-bit id bidirectional 16-bit ia unidirectional 16-bit 0 1-bit word 7 0 8-bit word 15 0 16-bit word signed / unsigned 31 16 15 0 32-bit word signed / unsigned 39 32 31 16 15 0 40-bit word signed / unsigned format minimum maximum fractional signed - 1 + 0.999969481 unsigned 0 + 0.99996948 integer signed - 32768 + 32767 unsigned 0 + 65535
14/66 ST18952 4.1 d950core registers pcdr the port control direction register defines the data direction of each port pin. after reset, pcdr default value is 0 (port pins are configured as inputs) pcsr the port control sensitivity register defines sensitivity of each port pin. after reset, pcsr default value is 0 (port pins are configured as level-sensitive). register function bx modulo base address for x-memory space mx modulo maximum address for x-memory space by modulo base address for y-memory space my modulo maximum address for y-memory space por port output register - 8lsb are significant, 8msb are undefined when reading pir port input register pcdr port control direction register pcsr port control sensitivity register 1514131211109876543210 --------p7dp6dp5dp4dp3dp2dp1dp0d bit function pid port pin direction 0: input port pin (def.) 1: output port pin bits 8 - 15 reserved (read: undefined, write: don't care) 1514131211109876543210 --------p7sp6sp5sp4sp3sp2sp1sp0s bit function pis port pin sensitivity 0: level sensitive (def.) 1: edge sensitive bits 8 - 15 reserved (read: undefined, write: don't care)
15/66 ST18952 5 memory 5.1 internal memory resource one 32 kword and two 8 kword single port memories are included on-chip: ? instruction memory on i space from address 0 to 32767 (32 k) ? x-data memory on x space from address 0 to 8191 (8 k) ? y-data memory on y space from address 0 to 8191 (8 k) one 512 word dual port memory is shared on x and y spaces, from addresses 8192 (8 k) to 8703 (8.5k). this is represented graphically below. note: the first 256 addresses of the y space are reserved for the d950 memory-mapped registers and for on-chip memory mapped peripherals. memory can be extended off-chip for all three spaces in two ways: 1: directly - accesses to program and data memories can be performed simulta- neously. insertion of wait-states is necessary in case of nominal frequency work. 2: through the bus switch unit - accesses to the different external spaces are mul- tiplexed and wait-states are added. the specific details on the operation of the bsu are described separately in obus switch unito on page 18. figure 5.1 memory mapping 0000 1fff 8k 32k ffff 64k 64k internal spram internal spram registers external internal spram external external all addresses are hexadecimal internal dpram internal dpram 21ff 8.5k 0100 64k 8k 8.5k ffff 8000 1fff ffff 21ff external memory is accessed directly or through the bus switch x-memory i-memory y-memory
16/66 ST18952 5.2 direct bus extension direct extension for i-memory the internal program memory is used from address 0 to 32767 (32 k). note, no detection is provided when an internal space is declared as an external one for the bsu. the i-bus direct transfer enable signal (idt_en) determines whether an access is made directly to external memory or via the bsu. if reset occurs with the mode signal set to `1' (select reset address to xfc00), then ? if idt_en input = 0: access to external memory is through the bsu ? if idt_en input = 1: access to direct external memory space iae/ibse/irde/iwre are always driven except in the case of an external hold request. note: an external coprocessor will work only when executing program in the external space. ide bus is an output only when a direct external write is detected. ide bus is an input in the case of: ? an external memory read ? dma (write) transfers between an external peripheral and internal memory direct extension for x-memory the internal x memory is used from address 0 to 8703 (8.5 k). it is extended with external memory from address 8704 (8.5k) to 65535 (64k) with the xe bus extension. the direct extension is managed by the bus switch unit. when the en_x bit of the bsu xer register (see oxer0/1: x-memory space control registerso on page 20) is set to `0', it generates only software wait-states and access is direct. if the en_x bit is set to `1', data goes via the bsu. x extension and bus switch share the same i/o's. direct extension for y-memory the internal y memory is used from address 0 to 8703 (8.5 k). it is extended with external memory from address 8704 (8.5 k) to 65535 (64 k) with the ye bus extension. address 0 to 256 of the y space are reserved for memory mapped registers. note: the bsu and x direct extension share the same i/o, therefore extension of ie through the bsu is not possible when direct extension is selected for x/y. some combinations of the en_i, en_x and en_y bits of the bsu control registers ier/xer/yer are not allowed, as shown in table 5.1 below.
17/66 ST18952 table 5.1 possible bsu register settings en_i en_x en_y operation allowed or forbidden 1 1 1 exchanges enabled on i/x/y spaces allowed 1 1 0 exchanges enabled on i and x spaces only dtack generation on y space allowed 1 0 1 exchanges enabled on i and y spaces only dtack generation on x space forbidden (x direct & i/y through bsu) 1 0 0 exchanges enabled on i space only dtack generation on x and y spaces forbidden (x direct & i through bsu) 0 1 1 exchanges enabled on x and y spaces only dtack generation on i space allowed 0 1 0 exchanges enabled on x space only dtack generation on i and y spaces allowed 0 0 1 exchanges enabled on y space only dtack generation on i and x spaces forbidden (x direct & y through bsu) 0 0 0 no exchange only dtack generation on i, x and y spaces allowed
18/66 ST18952 6 bus switch unit the three memory spaces can be extended off-chip through the bus switch unit (bsu) peripheral. the figure below shows the layout of the d950core bsu. figure 6.1 d950core bus switch unit 6.1 bsu operation the bsu recognizes a bus cycle when a bus extension strobe (ibse, xbse or ybse) goes active. the bsu decodes the address value to determine if an external memory access is requested on the i, x or y-bus and generates the appropriate signals on the external bus side. the bsu generates software wait-states, depending on the setting of the control register. if more than one external memory access is attempted at one instruction cycle, they are serviced sequentially in the following order: i-bus, x-bus, y-bus. each external access requires one basic instruction clock cycle (2 clkin cycles), extended by, at least, one wait-state (2 clkin cycles). the number of wait-states can be extended, either by software with the bsu control registers (see section 6.2), or by hardware with the dtack input signal. ea ed id ia yd ya xa xd d950core bus switch unit dtack as-dsp bsu_clk reset ird/xrd/yrd iwr/xwr/ywr ibs/xbs/ybs 16 16 16 16 internal memories & peripherals 16 16 16 16 p mem. x mem. y mem. 22 2 dtackin eyrd/ds eywr/rd eird/ds eiwr/rd exrd/ds exwr/rd vr02020a internal memories & peripherals internal memories & peripherals deid/dexd/deyd iid/i xd/iyd idt_en
19/66 ST18952 6.2 bsu control registers the bsu is programmed by six control registers mapped in the y-memory space. these define the type of memory used, internal to external boundary address crossing, exchange type (external direct or through the bsu) and software wait-states count. there are 2 registers per memory space, making it possible to define 2 sets of boundaries and wait state numbers. figure 6.2 default and user mapping examples the bsu control registers include a reference address on bits 4 to 9, where the internal/ external memory boundary value is stored (see figure 6.2), and software wait-states count on bits 0 to 3, allowing up to 16 wait-states. external addressing is recognized by comparing these address bits for each valid address from ia, xa and ya, to the reference address contained into the corresponding control register. if the address is greater or equal to the reference value, an external access proceeds. in the following register descriptions, `-' means reserved (read: 0, write: don't care). external inte rnal1 64k 63k 62k internal 0 defa ult mapping (reset) user mapping (can change by 1k step) value 1 value 0 value 1 value 0 exte rnal internal1 internal0 64k 0 0
20/66 ST18952 xer0/1: x-memory space control registers after reset, xer0/1 default values are 0x83ef/0x83ff yer0/1: y-memory space control registers after reset, yer0/1 default values are 0x83ef/0x83ffi ier0/1: instruction memory control registers after reset, ier0/1 default values are 0x83ef/0x83ff or 0xc3ef/0xc3ff (the en_i value depends on the idt_en input value 1514131211109876543210 im en_x - - - - xa15 xa14 xa13 xa12 xa11 xa10 w3 w2 w1 w0 bit function w3:0 wait state count (1 to 16) for off-chip access (x-memory space) xa15:10 x-memory space map for boundary on-chip or off-chip en_x enable for x-space data exchanges im intel/motorola 0: motorola type for memories 1: intel type for memories (default) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 im en_y - - - - ya15 ya14 ya13 ya12 ya11 ya10 w3 w2 w1 w0 bit function w3:0 wait state count (1 to 16) for off-chip access (y-memory space) ya15:10 y-memory space map for boundary on-chip or off-chip en_y enable for y-space data exchanges im intel/motorola 0: motorola type for memories 1: intel type for memories (default) 1514131211109876543210 im en_i ---- ia15 ia14 ia13 ia12 ia11 ia10 w3 w2 w1 w0 bit function w3:0 wait state count (1 to 16) for off-chip access (i-memory space) ia15:10 i-memory space map for boundary on-chip or off-chip en_i enable for i-space data exchanges im intel/motorola 0: motorola type for memories 1: intel type for memories (default)
21/66 ST18952 7 dma controller the dma controller manages data transfer between memories and external peripherals and has the following features: ? four independent dma channels ? transfers on x / y / i spaces (simultaneous transfers on x and y spaces) ? cycle stealing operation: ? 3 cycles for a single data transfer (+1cycle for transfers on i space) ? (n+2) cycles for an n-data block transfer (+1cycle for transfers on i space) ? each channel has: ? 3 signals: request (dmarq), acknowledge (dmack), interrupt request (dit) ? 4x16 bit registers for block transfer facilities ? fixed priority between the four channels (highest channel 0, lowest channel 3) the dma controller dmarq0-3 inputs and dmack0-3 outputs are available as primary inputs, in the case of sio inhibition. this is set by the dmar register (see odmar: dma management registero on page 44). figure 7.1 dma controller yd ya 16 16 d950core interr upt controller peripheral reset as-d sp hold holdack incy cle dma controller peripheral dmarq0 dmarq1 dmarq2 dmarq3 dmack0 dmack1 dmack2 dmack3 dtack dip_ena 16 16 16 16 ia id xa xd ird iwr ibs xr d xw r xb s yrd ywr ybs dit 0 dit1 dit2 dit3 dit_and 3 3 3 clk dma_clk
22/66 ST18952 7.1 dma operation the dma controller interface contains four independent channels allowing data transfer on i- memory space and simultaneous data transfer on x and y-memory spaces. when requests to transfer data on the same bus occur at the same time on different channels, the requests are concatenated to be acknowledged during the same transfer according to fixed priority. channel 0 has the highest priority ranging to channel 3 with the lowest priority. the dma transfer is based on a dsp cycle stealing operation: ? dma controller generates a `hold request'. ? the core sends back a `hold acknowledge' to the dma controller and enters the hold state (bus released). ? the dma controller manages the transfer and enters its idle state at the end of the transfer, until reception of a new dma request. the `hold request' signal is removed. the data transfer duration is n+2 cycles, split into: ? one cycle inserted at the beginning of the transfer when bus controls are released by the d950core, n cycles for the number of data words to be trans- ferred. ? another cycle is inserted at the end of the transfer when bus controls are released by the dma controller. single or block data can be transferred. the dma request signal (dmarq) can be either edge (single) or level (block) sensitive. data blocks can be transferred one data at a time using an edge sensitive request signal. a double buffering mechanism is available to deal with data blocks requiring the allocation of 2n addresses for the transfer of an n data block. an interrupt can be used to warn as-dsp that a predefined number of data have been transferred and are ready to be processed. interrupt requests are sent from the dma controller to the interrupt controller. the selected channels must be edge sensitive and the user has to define the proper priority.
23/66 ST18952 7.2 dma registers address registers two 16-bit registers (unsigned) are dedicated per channel for address transfer: ? dia: initial address. contains the initial address of the selected address bus (see dbc-bit of dgc register). ? dca: current address. contains the value to be transferred to the selected address bus (see dbc-bit of dgc register) during the next transfer. the different dca values are: note: see odaic: address/interrupt control registero on page 24 for dai and dla definitions counting registers two 16-bit registers (unsigned) per channel are dedicated for count transfer. for a transfer of an n data block, dic and dcc registers have to be loaded with n-1. when dcc content is 0 (valid transfer count), it is loaded with dic content for the next transfer. ? dic: initial count. contains the total number of transfers of the entire block ? dcc: current count. contains the remaining number of transfers required to fill the entire block. it is decremented after each transfer. the dcc values are: control registers three 16-bit control registers are dedicated to the dma controller interface. these are the general control register, the address interrupt control register and the mask sensitivity control register. they are detailed below. reset dai dla dcc = 0 dca(n+1) 1xxx0 0 0 x x dca(n) 0 1 0 x dca(n) + 1 0110 dca(n) + 1 0111dia reset dcc = 0 dca(n+1) 1x0 0 0 dca(n) - 1 0 1 dic
24/66 ST18952 dgc: general control register three bits are dedicated for each dma channel (bits 0 to 2 to channel 0, bits 4 to 6 to channel 1, bits 8 to 10 to channel 2, bits 12 to 14 to channel 3). (address = 0040, reset = 0000h, read/write). daic: address/interrupt control register four bits are dedicated for each dma channel (bits 0 to 3 to channel 0, bits 4 to 7 to channel 1, bits 8 to 11 to channel 2, bits 12 to 15 to channel 3). (address = 0042, reset = 0000h, read/write) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - drw3 dbc1 dbc0 - drw2 dbc1 dbc0 - drw1 dbc1 dbc0 - drw0 dbc1 dbc0 bit function dbc1/dbc0 bus choice for data transfer 00: x-bus (default) 01: y-bus 10: i-bus 11: reserved drwi data transfer direction 0: write access (default) 1: read access 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dai3 dla3 dip3 die3 dai2 dla2 dip2 die2 dai1 dla1 dip1 die1 dai0 dla0 dip0 die0 bit function diei enable interrupt 0: interrupt request output associated to channel i is masked (default) 1: interrupt request output associated to channel i is not masked dipi interrupt pending 0: no pending interrupt on channel i (default) 1: pending interrupt on channel i (enabled if dip_ena input is high) dlai: load address 0: dcai content incremented after each data transfer (default) 1: dcai content loaded with dia content if dcci value is 0, or dcai content incremented if dcci value is not equal to 0 daii address increment 0: dcai content unchanged (default) 1: dcai content modified according to dlai state
25/66 ST18952 dms: mask sensitivity control register two bits are dedicated to each dma channel (bits 0 and 1 to channel 0, bits 4 and 5 to channel 1, bits 8 and 9 to channel 2, bits 12 and 13 to channel 3). (address = 0041, reset = x3333h, read/write) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - dse3 dmk3 - - dse2 dmk2 - - dse1 dmk1 - - dse0 dmk0 bit function dmki dma mask 0: dma channel not masked 1: dma channel masked (default) dsei dma sensitivity 0: low level 1: falling edge (default)
26/66 ST18952 8 interrupt controller the interrupt controller (itc) can manage up to eight external interrupts. the interrupt controller has the following features: ? 8 independent interrupt sources, each one associated with: ? 16-bit programmable interrupt vector - provides the address of the first instruction of the interrupt routine associated with the source. ? mask bit, enabling each source to be activated or deactivated ? sensitivity bit (edge/level) ? 2-bit programmable priority level ? `pending interrupt' flag - displays the source waiting for service. this flag is writ- able to allow a software interrupt capability. ? interrupt processing whenever its priority level is higher than the current priority level. ? nested of up to 4 interrupts(the stack content is accessible in read or write). figure 8.1 d950core interrupt controller the interrupt controller itrq inputs can be connected to external interrupt requests or to internal peripheral requests, this is dependent on the setting of the port/interrupt control (picr) system register, see table on page 43 for details. the interrupt controller receives interrupt yd ya 16 16 d950core interrupt controller peripheral itrq1 it itack eoi ywr reset clk incycle it itack ywr yrd yrd eoi itrq0 itrq2 itrq3 itrq4 itrq5 itrq6 itrq7 as-dsp vr02020c
27/66 ST18952 requests from primary inputs p_itrq0-7 on its inputs itrq0-7 when bit 0-7 of the picr register is set to `0'. otherwise, the itrq0-7 input is connected to internal peripheral interrupt request output. each input can be programmed independently. 8.1 interrupt controller registers the interrupt controller interface is controlled by status and control registers mapped into the y-memory space. status registers are not write-protected. ivo0-7: interrupt vector0-7 address registers the ivo0-7 registers (one per external interrupt) contain the first address of the interrupt routine and are associated with the respective interrupt input itrq0-7. the register content of the interrupt under service is provided on the yd bus during the cycle following the itack falling edge. (address = 0020-0027, no reset value, read/write) icr: interrupt control register the icr register displays the current priority level and up to four stacked priority levels. (address = 0028, reset = 000bh, read/write)) 1514131211109876543210 ivi 15 ivi 14 ivi 13 ivi 12 ivi 11 ivi 10 ivi 9 ivi 8 ivi 7 ivi 6 ivi 5 ivi 4 ivi 3 ivi 2 ivi 1 ivi 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spl4 (2:0) spl3 (2:0) spl2 (2:0) spl1 (2:0) es cpl (2:0) bit function cpl current priority level (-1, 0, 1, 2 or 3) (default is 011) es empty stack flag 0: stack is used 1: stack is not used (default) spl1 3-bit 1st stacked priority level spl2 3-bit 2nd stacked priority level spl3 3-bit 3rd stacked priority level spl4 3-bit 4th stacked priority level
28/66 ST18952 the current priority levels available are shown in below. an interrupt request is acknowledged when its priority level (coded in the ipr register) is higher than the current priority level. in this case, the current priority level becomes the interrupt priority level and the previous current priority level is pushed onto the stack and displayed as stack priority level (spl)1. the process is repeated over a range of four interrupt requests and the four previous current stack priority levels are displayed on spl1, spl2, spl3 and spl4. if less than four interrupts are pushed onto the stack, the unused spl words are set to `000'. at the end of the interrupt routine, the priority levels are popped from the stack. the empty stack (es) flag is used to indicate whether the stack is used or not. the isp word of the isp register indicates the depth of the stack (see below). figure 8.2 icr and ispr operation priority level coding acceptable it level priority - 1 111 0,1,2,3 0 000 1,2,3 1 001 2,3 2 010 3 3 011 reserved 100 - 110 spl4 spl3 spl2 spl1 es cpl interrupt level 2 program program it2 program it3 it2 it3 interrupt level 3 xxxx1 -1 spl4 spl3 spl2 spl1 es cpl xxx-10 2 spl4 spl3 spl2 spl1 es cpl xx-120 3 01 2 isp isp isp icr ispr
29/66 ST18952 imr: interrupt mask/sensitivity register (address = 0029, reset = 5555h, read/write) each interrupt input itrq0-7 can be masked individually when the corresponding im0-7 bit is set. in this case any activity on the itrq0-7 pin is ignored. all im bits are set during dsp reset. itrq0-7 is active either on a low level when is0-7 is low (by default on reset) or on a falling edge when is0-7 is high. when itrq0-7 is active on a low level, it must stay low until the itack falling edge is sampled. ipr: interrupt priority register (address = 002a, reset = 0000h, read/write)) the ipr register contains the priority level of each itrq0-7 interrupt input. ip0-7 priority level is coded using two bits. the different values of ip are 0, 1, 2, 3 (0 lowest priority, 3 highest priority). when two itrq with the same priority level are requesting during the same cycle, the first acknowledged interrupt is the one corresponding to the lowest number (for example, itrq0 acknowledged prior to itrq3). 1514131211109876543210 is7 im7 is6 im6 is5 im5 is4 im4 is3 im3 is2 im2 is1 im1 is0 im0 bit function im interrupt mask 0: interrupt is not masked 1: interrupt is masked (default) is sensitivity 0: itrq is active on a low level (default) 1: itrq is active on a falling edge 1514131211109876543210 ip7(1:0) ip6(1:0) ip5(1:0) ip4(1:0) ip3(1:0) ip2(1:0) ip1(1:0) ip0(1:0) bit function ip interrupt priority level (0, 1, 2 or 3) (default is 0)
30/66 ST18952 ispr: interrupt stack pointer register (address = 002b, reset = 0000h, read/write) note: '-' is reserved (read: 0, write: don't care) ispr contains the number of stacked priority levels. if the ispr value is directly written, the spli/cpl values are modified. so the icr register content is no longer significant but the interrupt routine procedure is not affected. after reset, ispr default value is 0 isr: interrupt status register (address = 002c, reset = 0000h, read/write) note: ` -' is reserved (read: 0, write: don't care) an interrupt pending (ipe) bit is associated with each interrupt input. ipe is set when the interrupt request is recorded and is reset when the interrupt request is acknowledged (itack falling edge). when the user does not want to acknowledge any of the pending interrupt requests, the ipe flag of the ccr register must first be reset and then the isr register set to a0000o. when only some pending interrupt requests need to be acknowledged, the ipe bits of the other interrupt inputs must be reset. when the ipe bit is set by a direct register write an interrupt request will be generated irrespective of the state of the itrq pin. when the mask (im) bit is set, the corresponding ipe bit is reset. 1514131211109876543210 ------------- isp(2:0) bit function ispr number of stacked priority levels (0, 1, 2 or 3) 1514131211109876543210 - - - - - - - ipe7 ipe6 ipe5 ipe4 ipe3 ipe2 ipe1 ipe0 bit function ipe interrupt pending bit 0: reset when interrupt request is acknowledged (default) 1: set when interrupt request is recorded
31/66 ST18952 9 timers there are two timer (tim) units on the ST18952. the timers enable interrupts to be generated after predefined periods of time. each timer has the following features: ? 16 bits linear timer / 4 bits exponential prescaler ? counting between 16 bits astart valueo and 16 bits aend valueo ? counting period between 2 cycles and 2 32 cycles (50ns to 107s for a 40 mhz d950). note, 1 cycle = 2 mclk periods. ? 1 maskable interrupt request ? external counting clock input ? programmable functions: ? external / internal clock ? up / down counting ? continue / stop modes ? interrupt enable when bit 4 of the picr system register (see table ) is set to `1', tim0 interrupt request output is connected to the itrq4 input of the interrupt controller. when bit 5 of the picr register is set to `1', tim1 interrupt request output is connected to the itrq5 input of the interrupt controller. refer to chapter 8 for full details on the interrupt controller. after reset, the timers interrupt outputs are not connected. setting the timer enable (ten) bit of the timer control (tcr) register to `1' starts the timer. 9.1 timer registers tcr0-1: timer control register the timer control register (tcr) contains timer control information. (address = 0058/005c, reset value = 0000 h, read/write) 1514131211109876543210 (0) (0) (0) (0) (0) (0) tfp(3:0) itcm tie tcs tle tud ten bit function ten timer enable (bit 0) ? when ten = `0', the tim is disabled. ? when ten = `1', the tim is started. note : the timer must be disabled before the timer registers are configured, otherwise its behavior is not guaranteed. once configured it can be enabled.
32/66 ST18952 tsvr0-1: timer start value register (address = 0059/005d, reset value = 0000 h, read/write) tud timer up/down counting (bit 1) ? when tud = `0', the tim is counting `down' (reset value), i.e. the tcvr current value register content is decremented. ? when tud = `1', the tim is counting `up', i.e. the tcvr current value register content is incremented. tle timer load enable (bit 2) ? when the counter has reached its end value (tcvr = tevr), tcvr is (re)loaded with tsvr (`start value') register content when tle = `1'. ? when tle = `0' (reset value), the next state of tcvr depends on the tcs bit. tcs timer continue/stop (bit 3) ? when tle = `0' (no load) and when the counter has reached its end value (tcvr = tevr), the tcvr content continues to increment/decrement according to tud bit when tcs = `1' (continue mode). ? when tcs = `0' (stop mode - reset value), tcvr is stopped and content is frozen. tie timer interrupt enable (bit 4) ? when the counter has reached its end value (tcvr = tevr), an interrupt request is generated on tir output when tie = `1'. ? when tie = `0' (reset value), tir output is disabled (=`1'). tcm timer cock mode (bit 5) ? when tcm = `0' (reset value), the tcvr clock is derived from internal mclk clock according to tfp bits. ? when tcm = `1', the tcvr clock is the external eclk clock. tfp(3:0) timer frequency prescaler (bits 9-4; tfp(3) = msb) ? when tcm = `0' (internal clock), the tcvr register clock is derived from the mclk clock input by dividing mclk by 2 (2+ tfp) . the coding is as follows: tfp = 0h prescaler by 2 (reset value) mclk divided by 4 tfp = 1h prescaler by 4 mclk divided by 8 tfp = 2h prescaler by 8 mclk divided by 16 -... tfp = fh prescaler by 2 16 mclk divided by 2 17 bits 10-11 reserved and must be written as'0' bits 12-15 unused and read as'0' 1514131211109876543210 tsv 15 tsv 14 tsv 13 tsv 12 tsv 11 tsv 10 tsv 9 tsv 8 tsv 7 tsv 6 tsv 5 tsv 4 tsv 3 tsv 2 tsv 1 tsv 0 bit function tsv(15:0) timer start value (bits15-0, tsv15 is msb
33/66 ST18952 tsvr contains the data to be transferred to the tcvr current value register when: 1: ten = `1' (tim enable) tle = `1' (tim load enable) tcvr = tevr (count period finished) tcs = `1' (stop mode disabled). 2: first counting clock rising edge after timer start (timer starts on rising edge of ten ).??? tevr0-1: timer end value register (address = 005a/005e, reset value = 0000 h, read/write)) tevr contains the data to be compared to the tcvr current value register. tcvr0-1: timer current value register (address = 005b/005f, reset value = 0000 h, read only) tcvr contains the current counting value. when tcvr = tevr, the tcvr content is changed according to table 9.1. the tcvr clock is derived from internal mclk clock according to tfp bits when tcm = `0' or is equal to external eclk clock when tcm = `1'. note: timers external clocks are not directly user accessible. they are connected to incycle. 1514131211109876543210 tev 15 tev 14 tev 13 tev 12 tev 11 tev 10 tev 9 tev 8 tev 7 tev 6 tev 5 tev 4 tev 3 tev 2 tev 1 tev 0 bit function tev(15:0) timer end value (bits15-0 - tev(15) = msb 1514131211109876543210 tcv 15 tcv 14 tcv 13 tcv 12 tcv 11 tcv 10 tcv 9 tcv 8 tcv 7 tcv 6 tcv 5 tcv 4 tcv 3 tcv 2 tcv 1 tcv 0 bit function tcv(15:0) timer current value (bits15-0 - tcv(15) = msb)
34/66 ST18952 table 9.1 counting modes tle tcs tcvr(n) = tevr tud ten tcvr(n+1) description x x x x 0 tcvr(n) tim disable x 0 1 x 1 stop x x 0 0 tcvr(n)-1 decrement 0 1 1 decrement (continue) x x 0 1 tcvr(n)+1 increment 0 1 1 increment (continue) 1 1 1 x tsvr load
35/66 ST18952 10 sio the ST18952 has two synchronous serial input/output (sio) ports which link to serial devices such as codecs and to other processors. the sio ports work in dma mode. sio0 uses channels 0 and 1 of the dma controller, sio1 uses channels 2 and 3. the chip must be configured for sio using the dmar system register (odmar: dma management registero on page 44). for sio port 0, bits 1 and 0 of the dmar register must be reset to inhibit external dma requests (1 and 0) and to allow sio port 0 communication with the outside. for sio port 1, bits 3 and 2 of the dmar register must be reset to inhibit external dma requests (3 and 2) and to allow sio port 1 communication with the outside. the sio ports have the following features: ? double-buffered full-duplex operation ? frequency up to d950 input clock (33 mbps for 66 mhz d950) ? programmable functions ? word length: 8/16 bits (msb first) ? up to 8 words per frame ? frequency prescaler (by 1 or 3) and divider (by 2 1 to 2 8 ) ? synchronization signal: bit length/word length, delayed/not delayed, active level ? clock signal: internal/external, active edge ? 4 status flags / 2 enabled interrupt requests ? data transfers between sio and memories using dma
36/66 ST18952 10.1 sio registers each sio port has the following set of registers. stb0-3: sio transmit buffers stb0-3 buffers contain the data to be transferred to the sio transmit shift register. sio0 registers ? (stb0: address = 0068h, reset value = 0000 h, write only) ? (stb1: address = 0069h, reset value = 0000 h, write only) ? (stb2: address = 006ah, reset value = 0000 h, write only) ? (stb3: address = 006bh, reset value = 0000 h, write only) sio1 registers ? (stb0: address = 00e8 h, reset value = 0000 h, write only) ? (stb1: address = 00e9 h, reset value = 0000 h, write only) ? (stb2: address = 00ea h, reset value = 0000 h, write only) ? (stb3: address = 00eb h, reset value = 0000 h, write only) srb0-3: sio receive buffers srb0-3 buffers contain the data transferred from the sio receive shift register. sio0 registers ? (srb0: address = 006ch, reset value = xxxx h, read only) ? (srb1: address = 006dh, reset value = xxxx h, read only) ? (srb2: address = 006eh, reset value = xxxx h, read only) ? (srb3: address = 006fh, reset value = xxxx h, read only) sio1 registers ? (srb0: address = 00ec h, reset value = xxxx h, read only) ? (srb1: address = 00ed h, reset value = xxxx h, read only) ? (srb2: address = 00ee h, reset value = xxxx h, read only) ? (srb3: address = 00ef h, reset value = xxxx h, read only)
37/66 ST18952 scor: sio sequence control register (sio0 address = 0070h, reset value = 0000h, read/write) (sio1 address = 00f0 h, reset value = 0000h, read/write) scr: sio control register (sio0 address = 0062h, reset value = 0000h, read/write) (sio1 address = 00e2h, reset value = 0000h, read/write) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (0) seq(1:0) bit function seq(1:0) four sio sequences (defining the time slots order) are available: seq=00 data/data/data/data seq=01 data/control/data/control seq=10 data/data/control/control seq=11 control/control/control/control data time slots are transferred using the dma controller, and control time slots are trans- ferred using sio buffers. bits 2-15 unused and read as `0' 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (0) sll smen srie stie swn(2:0) ssm ssal ssl sce scsd swl sms 00 0 0 11 011 0000 0 00 bit function sms sio mode select: must be set to 0 (normal mode) swl sio word length swl = `0' word length is 16 bits (reset value) swl = `1' word length is 8 bits scsd sio clock/synchro direction determines whether sck clock and sfs frame synchro signals are generated externally or internally scsd = `0' generated externally (reset value) scsd = `1' generated internally sce sio clock edge sce = `0' sck rising edge active (reset value) sce = `1' sck falling edge active ssl sio frame syncro length generated in a bit-length manner (active for one clock cycle) when ssl='0' (reset value) or in a word-length manner (active for 8 or 16 clock cycles dep. on swl bit) when ssl='1'. ssal sio frame synchro active level ssal = `0' sfs high level active (reset value) ssal = `1' sfs low level active
38/66 ST18952 scr writes must be made when the sio is disabled (sen bit of the sio enable register is `0')sms: ssm sio frame synchro mode the sfs frame synchro is generated one clock cycle before the first data of the frame (delayed mode) when ssm = `0' (reset value) or when first data is transmitted/received (non-delayed mode) when ssm = `1'. swn(2:0) sio word number (swn(2) = msb) swn determines the number of words inserted in the frame (up to 8). the coding is as follows: swn = a0o -> 1 time slot swn = a1o -> 2 time slots ... swn = a7o -> 8 time slots the reset value is swn = a0o stie sio transmit interrupt enable ? when stie = `1', interrupt request generated on the sti output when stde flag = `1'. ? when stie = `0' (reset value), the sti output is disabled (`1') srie sio receive interrupt enable ? when srie = `1', interrupt request generated on sri output when the srdf flag = `1'. ? when srie = `0' (reset value), the sri output is disabled (`1') smem sio microwire enable: must be set to 0 (normal mode) sll sio local loop ? when sll = `1', the std output is internally linked to the srd input. this allows the sio behavior to be checked without providing data on the srd input. ? when sll = `0' (reset value), the srd input is enabled bits 15-14 unused and are read as `0' bit function sms sio mode select: must be set to 0 (normal mode)
39/66 ST18952 sfr: sio frequency register (sio0 address = 0063h, reset value = 0000h, read/write) (sio1 address = 00e3 h, reset value = 0000h, read/write) sfr writes must be made when the sen bit of the ser register is `0' (sio disabled) ser: sio enable register (sio0 address = 0064h, reset value = 0000h, read/write) (sio1 address = 00e4 h, reset value = 0000h, read/write) 1514131211109876543210 (0) 0 sfd(2:0) sfp bit function sfp sio frequency prescaler ? when the sck clock is generated internally (scsd bit of the scr register is set to `1'), it is derived from the mclk clock input by first prescaling mclk by 1 (sfp = `0' reset value) or by 3 (sfp = `1'). sfd(2:0) sio frequency divider (bits 3-1; sfd(2) = msb) ? when the sck clock is generated internally (scr/scsd = `1'), it is derived from the mclk clock input by second dividing mclk by 2 (1 + sfd) . sfd = a0o divided by 2 (reset value) sfd = a1o divided by 4 sfd = a2o divided by 8 ... sfd = a7o divided by 256 bits 5 and 4 reserved and must be written as `0' bits 15 to 6 unused and read as `0' 1514131211109876543210 (0) sen bit function sen sio enable ? when sen = `0', sio is disabled (reset value). scr and sfr writes must be made when sen = `0'. ? when sen = `1', the sio is enabled. bits 15 to 1 unused and read as `0'
40/66 ST18952 ssr: sio status register (sio0 address = 0065h, reset value = 0000 h, read only) (sio1 address = 00e5h, reset value = 0000 h, read only) 1514131211109876543210 slra(7:0) scwn(2:0) 0 srov srdf stun stde bit function stde sio transmit data empty ? stde is set when the content of the stdr data register is transferred into the trans- mit shift register signalling that the stdr data register is ready to be receive the next word to be transmitted. ? if the stie enable bit is set, an interrupt request occurs on the sti output (sti is low for 1 mclk cycle) when stde is set. stun sio transmit underrun ? stun is set when the transmit shift register is empty and the stdr data register has not been filled by the dsp. ? if another frame syncho occurs, the content of the stdr data register is transferred again into the transmit shift register and the previous word is re-transmitted. srdf sio receive data full ? srdf is set when the content of the receive shift register has been transferred into the srdr data register, signalling a new word receive. the srdr data register is ready to be read by the dsp. ? if the srie enable bit is set, an interrupt request occurs on the sri output (sri is low for 1 mclk cycle) when srdf is set. srov sio receive overrun ? srov is set when the receive shift register is ready to be transferred into the srdr data register, which has not been read by the dsp. ? if another frame syncho occurs, the content of the receive shift register is transferred into the srdr data register and the previous content of srdr is lost. bit 4 unused and read as `0' scwn(2:0) sio current word number (scwn(2) = msb) ? in normal and microwire modes, scwn contains the current word number value since the last frame synchro. in tdm mode, scwn determines the current slot number value since the last frame synchro. scwn = 0 -> 1st sub-frame / time slot scwn = 1 -> 2nd sub-frame / time slot ... scwn = 7 -> 8th sub-frame / time slot slra(7:0) sio last received address (bits 15-8) must write 0.
41/66 ST18952 stdr: sio transmit data register (sio0 address = 0060h reset value = 0000h, write only) (sio1 address = 00e0h reset value = 0000h, write only) srdr: sio receive data register (sio0 address = 0061h, reset value = xxxxh, read only) (sio1 address = 00e1h, reset value = xxxxh, read only) 1514131211109876543210 std 15 std 14 std 13 std 12 std 11 std 10 std 9 std 8 std 7 std 6 std 5 std 4 std 3 std 2 std 1 std 0 bit function std(15:0) sio transmit data (std(15) = msb) ? std contains the data to be transferred to the transmit shift register at the beginning of the next sub-frame or time slot. the data is transmitted msb first. ? when 8-bit data format (scr/swl = `1') is used, the byte must be left justified (written on bits 7 to 0, bits 15 to 8 are ignored). the msb is bit 7. 1514131211109876543210 srd 15 srd 14 srd 13 srd 12 srd 11 srd 10 srd 9 srd 8 srd 7 srd 6 srd 5 srd 4 srd 3 srd 2 srd 1 srd 0 bit function srd(15:0) sio receive data (srd(15) = msb) ? srd contains the data transferred from the receive shift register at the end of the last sub-frame or time slot. the data is right justified (msb = bit 15). ? when 8-bit data format (scr/swl = `1') is used, the byte is left justified (significative on bits 7 to 0, bits 15 to 8 are ignored). the msb is bit 7.
42/66 ST18952 11 external coprocessor dedicated co-processors can be designed by sgs-thomson, by customer request. the d950core instruction set includes two co-processor dedicated one-word instructions, allowing one (cops) or two (copd) parallel data moves between x or y-memory space and co-processor registers. while a co-processor instruction is decoded by the d950core, the vci output is asserted high, indicating to the co-processor that such an instruction will be executed at the next cycle. control and status registers, at least one of each, must be included in the co-processor. this allows initialization in various operating modes and gives information to the d950core on operations in progress and status. an external coprocessor can only be used when program and data bus extensions are enabled. 12 system control system control is provided by glue logic and performs the following functions: ? control of bus extensions and multiplexing of bsu and x extension io's. ? interrupt vector management (in case of interrupt controller inhibition) ? control of input clock frequency ? test control management ? bus requests (hold) arbitration ? buffering
43/66 ST18952 12.1 system registers there are 4 system registers: cmr clock management register; picr port/interrupt control register; intr interrupt vector register; and dmar dma management register. the registers are y memory-mapped. picr: port/interrupt control register the interrupt controller itrq inputs can be connected to external interrupt requests or to internal peripheral requests, this is dependent on the setting of the port/interrupt control (picr) system register. the interrupt controller receives interrupt requests from primary inputs p_itrq0-7 on its inputs itrq0-7 when bit 0-7 of the picr register is set to `0'. otherwise, the itrq0-7 input is connected to the internal peripheral interrupt request output. each input can be programmed independently. (address = 0049 h, reset value = 0000 h, read/write) note: p_itrq0-7 primary i/os are used for external interrupt requests and for the d950 8-bit general purpose parallel port (p0-7). depending on the picr value and the programming of 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nm io io tim1 tim0 dma3 dma2 dma1 dma0 bit function dma0 0: itc itrq0 connected to p_itrq0 primary i/o 1: itc itrq0 connected to dma dit0 output dma1 0: itc itrq1 connected to p_itrq1 primary i/o 1: itc itrq1 connected to dma dit1 output dma2 0: itc itrq2 connected to p_itrq2 primary i/o 1: itc itrq2 connected to dma dit2 output dma3 0: itc itrq3 connected to p_itrq3 primary i/o 1: itc itrq3 connected to dma dit3 output tim0 0: itc itrq4 connected to p_itrq4 primary i/o 1: itc itrq4 connected to timer0 interrupt request output tim1 0: itc itrq5 connected to p_itrq5 primary i/o 1: itc itrq5 connected to timer1 interrupt request output io 0: itc itrq6 connected to p_itrq6 primary i/o 1: itc itrq6 is not used (connected to vdd) io 0: itc itrq7 connected to p_itrq7 primary i/o 1: itc itrq7 is not used (connected to vdd) nm 0: normal mode. 1: itc inhibited (bit 7-0 unused). d950core it input directly connected to p_itrq-7 primary i/o. bits15:9 unused
44/66 ST18952 the d950 parallel port (input or output), the interrupt controller can be fed by the d950 parallel port output. intr: interrupt vector register (address = 004ah, reset = 0000h, write only) in the case of the interrupt controller being inhibited (bit 8 of the picr register set to `1'), the intr register controls interrupt vector generation. this register must be initialized (intr=0000 after reset) and can not be read. after reset, itc inputs are fed with external interrupt requests. dmar: dma management register the dma controller dmarq0-3 inputs and dmack0-3 outputs are available as primary inputs, in case of sio inhibition. this is set by the system register dmar. (address: 004bh, reset = 0000h, read/write): outputs dit0-3 are connected to the interrupt controller inputs itrq0-3 (via picr system register described above). hold dma output is connected to hold d950 input through an arbitration module, which takes into account external hold requests and manages holdack generation to the right hold sender. after reset, dma requests come from the sio. 1514131211109876543210 not used d3 d2 d1 d0 bit function d0 0: dmarq0 connected to dmarq0 sio0 and dmack0 connected to dmack0 sio0 1: dmarq0 connected to external dmarq0 input called (dmarq0_srd0) and dmack0 connected to external dmack0 input called (dmack0_std0) d1 0: dmarq1 connected to dmarq1 sio0 and dmack1 connected to dmack1 sio0 1: dmarq1 connected to external dmarq1 input called (dmarq1_sck0) and dmack1 connected to external dmack1 input called (dmack1_sfs0) d2 0: dmarq2 connected to dmarq0 sio1 and dmack2 connected to dmack0 sio1 1: dmarq2 connected to external dmarq2 input called (dmarq2_srd1) and dmack2 connected to external dmack2 input called (dmack2_std1) d3 0: dmarq3 connected to dmarq1 sio1 and dmack3 connected to dmack1 sio1 1: dmarq3 connected to external dmarq3 input called (dmarq3_sck1) and dmack3 connected to external dmack3 input called (dmack3_sfs1) bit 4 - 15 not used
45/66 ST18952 note: use of an external dma controller is possible. in this case, only exchanges between external peripherals and external memories are allowed. all direct extension buses are isolated. 12.2 clocks a 27 mhz crystal can be used with the on-chip oscillator and pll to provide the d950 clock input. the pll module multiplies the oscillator frequency by a factor of 10 and generates a 270 mhz signal. a programmable divisor is connected to the pll output to generate the d950 clock input. the division range is 2 to 256 and can be programmed by writing to the cmr clock management system register. cmr: clock management register (address = 0048h, reset = 0000h, read/write) the oscillator and pll can be bypassed by setting the clk_mode pin to `1'. in this case the d950 clkin input receives the clock signal directly from the mclk input. 1514131211109876543210 reserved d2 d1 d0 d2 d1 d0 division factor output clock frequency 0 0 0 2 135 mhz 0 0 1 4 67.5 mhz 0 1 0 8 33.74 mhz 0 1 1 16 16.88 mhz 1 0 0 32 8.44 mhz 1 0 1 64 4.22 mhz 1 1 0 128 2.11 mhz 1 1 1 256 1.05 mhz
46/66 ST18952 13 jtag ieee 1149.1 test access port the test access port (tap) conforms to ieee standard 1149.1. the tap consists of five pins: tms , tck , tdi , tdo and trst . tdo can be overdriven to the power rails, and tck can be stopped in either logic state. the instruction register is 8 bits long, with no parity, and the pattern a00000001o is loaded into the register during the capture-ir state. there are three defined public instructions, see table 13.1. all other instruction codes are reserved. table 13.1 instruction codes notes 1: msb... lsb; lsb closest to tdo 14 emulation unit the emulation unit (emu) performs to emulation and test fuctions through the external ieee 1149.1 jtag interface. refer to ojtag ieee 1149.1 test access porto on page 46. the emulation and test operations are controlled by the jtag test access port (tap) and the emulator by means of dedicated control i/os. emulation mode can entered in one of two ways: ? asserting erq input pin low. ? meeting a valid breakpoint condition or executing an instruction in single step mode. the pc board emulator is able to display the processor status (memories and registers) and restore the context. the emulation resources (see figure 14.1) include: ? four breakpoint registers (bp0, bp1, bp2, bp3) which can be affected by program or data memory. ? breakpoint counter (bpc). ? program counter trace buffer (pcb) able to store the address of the 6 last executed instructions. ? three control registers for breakpoint condition programming. instruction code 1) instruction selected register 04h idcode identification 08h emu d950 ioscan ffh bypass bypass
47/66 ST18952 ? control logic for instruction execution through the pc-board emulator control. figure 14.1 emulation block diagram the emulation controller interface (see table 2.8 and table 2.9 on page 8) include pins of different types: ? erq, idle and snap are used by the emulator tools. ? haltack indicates that the processor is halted in emulation mode. ? aiebp, axebp and ayebp may be used to set additional conditions for break- point validation on the respective ia/xa/ya buses. bp registers comparators xa / ya xd / yd ia control registers control logic pc trace erq, idle, snap rd/wr d950 tap ia
48/66 ST18952 15 electrical specifications in the following tables tbd indicates `to be defined'. 15.1 dc absolute maximum ratings table 15.1 dc absolute maximum ratings 15.2 dc electrical characteristics junction temperature: -40oc to +125oc table 15.2 dc electrical characteristics symbol parameter value unit v dd supply voltage -0.3 / 3.9 v v in input voltage -0.3 / 3.9 v t a operating junction temperature range -40 / +125 o c t stg storage temperature range -55 / +150 o c symbol parameter min typical max unit v dd power supply 2.7 3.3 3.6 v v il input low level 0.3*v dd v v ih input high level 0.8*v dd v v ol output low level 0.4 v v oh output high level 0.85*v dd v i dd operating current tbd ma i sb stand-by current tbd m a
49/66 ST18952 15.3 ac characteristics the following timings are based on simulations and may change when full characterisation is completed. clocks electrical characteristics figure 15.1 clock timing diagram table 15.3 clock timing data no parameter min (ns) typ (ns) max (ns) t0 master clock cycle time 7.5 t3 clkout high delay 4.0 t4 clkout low delay 3.3 t5 incycle high delay -0.1 t6 incycle low delay -0.5 t0 mclk clkout incycle t3 t5 t4 t6
50/66 ST18952 reset electrical characteristics figure 15.2 reset timing diagrams table 15.4 reset timing data no parameter min (ns) typ (ns) max (ns) t0 master clock cycle time 7.5 t7 reset low setup 2.4 t8 reset_out low delay 1.7 t9 reset high setup nc t10 reset_out high delay 1.9 clkout mclk t8 t7 t0 reset reset_out x x clkout mclk t10 t0 reset reset_out t9
51/66 ST18952 bus control electrical characteristics figure 15.3 bus control timing diagram clkout mclk t0 dtack t11 t12 t13 incycle
52/66 ST18952 table 15.5 bus control timing data control i/o electrical characteristics figure 15.4 control i/o timing diagram table 15.6 control i/o timing diagram no parameter min (ns) typ (ns) max (ns) t0 master clock cycle time 7.5 t11 dtack high setup t0/4 t12 dtack low setup t0/4 t13 dtack high hold 0 no parameter min (ns) typ (ns) max (ns) t0 master clock cycle time 7.5 t14 control_in setup 6.0 t15 control_out high/low delay 3.0 clkout mclk t15 t0 control_in control_out t14
53/66 ST18952 instruction bus electrical characteristics figure 15.5 instruction bus timing diagram table 15.7 instruction bus timing data no parameter min (ns) typ (ns) max (ns) t0 master clock cycle time 7.5 t27 iae valid delay 1.9 t28 iae hold time 1.1 t29 ibse low delay 0.3 t30 ibse high delay 0.0 t31 ide high to lo z delay tbd t32 ide valid delay tbd t33 ide hold time 1.2 t34 iwre low delay t0/2 + 1.6 t35 iwre high delay 0.6 t36 ide setup 5.8 t37 ide hold -4.5 t38 irde low delay t0/2 + 0.5 t39 irde high delay 0.6 incycle t0 t27 mclk iae ibse ide iwre ide irde xx x x t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 clkout
54/66 ST18952 x-data bus electrical characteristics figure 15.6 x-data bus timing diagram table 15.8 x-data bus timing data no parameter min (ns) typ (ns) max (ns) t0 master clock cycle time 7.5 t40 ea_xae valid delay t0+3.7 t41 ea_xae hold time 2.7 t42 xbse low delay 0.1 t43 xbse high delay -0.2 t44 ed_xde high to low z delay tbd t45 ed_xde valid delay t0+3.9 t46 ed_xde hold time 0.3 t47 xwre_exwr low delay t0+2.7 t48 xwre_exwr high delay 0.4 t49 ed_xde setup 6.5 t50 ed_xde hold -5.0 t51 xrde_exrd low delay t0+2.6 t52 xrde_exrd high delay -0.7 incycle t0 t40 mclk ea_xae xbse ed_xde xwre_exwr ed_xde xrde_exrd xx x x t41 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 clkout
55/66 ST18952 y-data bus electrical characteristics figure 15.7 y-data bus timing diagram table 15.9 y-data bus timing data no parameter min (ns) typ (ns) max (ns) t0 master clock cycle time 7.5 t53 yae_sa valid delay 3.5 t54 yae_sa hold time 2.6 t55 ybse low delay 0.1 t56 ybse high delay 0.3 t57 yde_sd high to lo z delay tbd t58 yde_sd valid delay t0+3.5 t59 yde_sd hold time 0.5 t60 ywre low delay t0+1.7 t61 ywre high delay 0.5 t62 yde_sd setup 7.9 t63 yde_sd hold -5.2 t64 yrde low delay t0+1.2 t65 yrde high delay 0.6 incycle t0 t53 mclk yae_sa ybse yde_sd ywre yde_sd yrde xx x x t54 t55 t56 t57 t58 t59 t60 t61 t62 t63 t64 t65 clkout
56/66 ST18952 bus switch electrical characteristics (intel mode) figure 15.8 bus switch timing diagram (intel mode) table 15.10 y-data bus switch timing data no parameter min (ns) typ (ns) max (ns) t0 master clock cycle time 7.5 t66 ea_xae valid delay 4.4 t67 ea_xae hold time 3.3 t68 ed_xde high to lo z delay tbd t69 ed_xde valid delay t0+2.4 t70 ed_xde hold time 1.6 t71 ei/x/ywr low delay t0+2.3 t72 ei/x/ywr high delay 1.9 t73 ed_xde setup 7.1 t74 ed_xde hold -5.8 t75 ei/x/yrd low delay t0+2.1 t76 ei/x/yrd high delay -1.5 t66 ea_xae ed_xde ei/x/ywr ed_xde ei/x/yrd xx x t67 t68 t69 t70 t71 t72 t73 t74 t75 t76 x data_out incycle t0 mclk clkout
57/66 ST18952 16 y space memory mapping 16.1 memory map figure 16.1 ST18952 memory map 16.2 serial input/output registers table 16.1 sio1 registers reserved ffff-ffd3 external y memory space ffd2-3000 internal y dual port ram 21ff-2000 internal y ram 1fff-1000 reserved 00ff-00f1 serial input/output1 00f0-00e0 reserved 00df-0071 serial input/output 0 0070-0060 timer1 005f-005c timer0 005b-0058 reserved 0057-0056 bus switch unit 0055-0050 reserved 004f-004c system control 004b-0048 reserved 0047-0043 dma controller 0042-0030 reserved 002f-002d interrupt controller 002c-0020 reserved 001f-0019 emulator peripheral 0018-0010 reserved 000f-0008 d950core 0007-0000 address (hex) register description 00f1-00ff reserved 00f0 scor sio control register 00ef srb3 sio receive buffer 00ee srb2 sio receive buffer 00ed srb1 sio receive buffer 00ec srb0 sio receive buffer 00eb stb3 sio transmit buffer
58/66 ST18952 table 16.2 sio0 registers 00ea stb2 sio transmit buffer 00e9 stb1 sio transmit buffer 00e8 stb0 sio transmit buffer 00e7 -/-/stsr reserved - unused on the ST18952 00e6 -/sar/smr reserved - unused on the ST18952 00e5 ssr status 00e4 ser enable 00e3 sfr frequency 00e2 scr control 00e1 srdr receive data 00e0 stdr transmit data address (hex) register description 0071-00df reserved 0070 scor sio control register 006f srb3 sio receive buffer 006e srb2 sio receive buffer 006d srb1 sio receive buffer 006c srb0 sio receive buffer 006b stb3 sio transmit buffer 006a stb2 sio transmit buffer 0069 stb1 sio transmit buffer 0068 stb0 sio transmit buffer 0067 -/-/stsr reserved - unused on the ST18952 0066 -/sar/smr reserved - unused on the ST18952 0065 ssr status 0064 ser enable 0063 sfr frequency 0062 scr control 0061 srdr receive data 0060 stdr transmit data
59/66 ST18952 16.3 timer registers table 16.3 timer1 registers table 16.4 timer0 registers 16.4 bus switch unit registers 16.5 system control registers address (hex) register description 005f tcvr timer current value register 1 005e tevr timer end value register 1 005d tsvr timer start value register 1 005c tcr timer control register 1 address (hex) register description 005b tcvr timer current value register 0 005a tevr timer end value register 0 0059 tsvr timer start value register 0 0058 tcr timer control register 0 address (hex) register description 0055 yer1 external y-bus control register 1 0054 xer1 external x-bus control register 1 0053 ier1 external i-bus control register 1 0052 yer0 external y-bus control register 0 0051 xer0 external x-bus control register 0 0050 ier0 external i-bus control register 0 address (hex) register description 004b dmar dma management register 004a intr interrupt vector register 0049 picr port/interrupt interface control register 0048 cmr clock management register
60/66 ST18952 16.6 dma controller registers 16.7 interrupt controller registers address (hex) register description 0042 daic dma address / interrupt control 0041 dms dma mask sensitivity 0040 dgc dma general control 003f dcc3 dma channel 3 current count 003e dcc2 dma channel 2 current count 003d dcc1 dma channel 1 current count 003c dcc0 dma channel 0 current count 003b dic3 dma channel 3 initial count 003a dic2 dma channel 2 initial count 0039 dic1 dma channel 1 initial count 0038 dic0 dma channel 0 initial count 0037 dca3 dma channel 3 current address 0036 dca2 dma channel 2 current address 0035 dca1 dma channel 1 current address 0034 dca0 dma channel 0 current address 0033 dia3 dma channel 3 initial address 0032 dia2 dma channel 2 initial address 0031 dia1 dma channel 1initial address 0030 dia0 dma channel 0 initial address 002c isr interrupt status register 002b ispr interrupt stack pointer register 002a ipr interrupt priority register 0029 imr interrupt mask/sensitivity register 0028 icr interrupt control register 0027 iv7 interrupt vector 7 address 0026 iv6 interrupt vector 6 address 0025 iv5 interrupt vector 5 address 0024 iv4 interrupt vector 4 address 0023 iv3 interrupt vector 3 address 0022 iv2 interrupt vector 2 address 0021 iv1 interrupt vector 1 address 0020 iv0 interrupt vector 0 address
61/66 ST18952 16.8 emulation unit registers 16.9 d950core control registers address (hex) register description 0018 pcb pc trace buffer 0017 bpc breakpoint counter 0016 bp3 breakpoint register 3 0015 bp2 breakpoint register 2 0014 bp1 breakpoint register 1 0013 bp0 breakpoint register 0 0012 bc1 breakpoint control register 1 0011 bc0 breakpoint control register 0 0010 ecs emu control and status register address (hex) register description 0007 pcsr port control sensitivity register 0006 pcdr port control direction register 0005 pir port input register 0004 por port output register 0003 my y-memory space modulo max address 0002 by y-memory space modulo base address 0001 mx x-memory space modulo max address 0000 bx x-memory space modulo base address
62/66 ST18952 17 ST18952 package specifications 17.1 208 pin pqfp pinout 1 iae<15> 53 dmack0_std0 105 dtack 157 ea_xae<11> 2 iae<14> 54 dmack1_sfs0 106 ed_xde<0> 158 ea_xae<12> 3 iae<13> 55 dmack2_std1 107 ed_xde<1> 159 ea_xae<13> 4 iae<12> 56 yae<0> 108 ed_xde<2> 160 ea_xae<14> 5 iae<11> 57 yae<1> 109 vdd 161 gnd 6 gnd 58 yae<2> 110 gnd 162 vdd 7 vdd 59 yae<3> 111 ed_xde<3> 163 ea_xae<15> 8 iae<10> 60 vdd 112 extal 164 vci 9 iae<9> 61 gnd 113 xtal 165 tms 10 iae<8> 62 yae<4> 114 gnd 166 tdo 11 iae<7> 63 yae<5> 115 vdd 167 tdi 12 iae<6> 64 yae<6> 116 ed_xde<4> 168 tck 13 iae<5> 65 yae<7> 117 ed_xde<5> 169 gnd 14 iae<4> 66 yae<8> 118 ed_xde<6> 170 vdd 15 iae<3> 67 yae<9> 119 vdd 171 vdd 16 iae<2> 68 yae<10> 120 gnd 172 gnd 17 iae<1> 69 yae<11> 121 ed_xde<7> 173 stacky 18 iae<0> 70 yae<12> 122 ed_xde<8> 174 stackx 19 gnd 71 yae<13> 123 ed_xde<9> 175 snap 20 vdd 72 vdd 124 vdd 176 trst 21 ide<15> 73 gnd 125 gnd 177 reset_out 22 ide<14> 74 yae<14> 126 ed_xde<10> 178 reset 23 ide<13> 75 yae<15> 127 ed_xde<11> 179 lp 24 ide<12> 76 ybse 128 ed_xde<12> 180 lpack 25 ide<11> 77 vdd 129 ed_xde<13> 181 p_itrq<7> 26 ide<10> 78 gnd 130 ed_xde<14> 182 gnd 27 ide<9> 79 yrde 131 ed_xde<15> 183 vdd 28 ide<8> 80 ywre 132 xbse 184 p_itrq<6> 29 vdd 81 yde<0> 133 xrde_exrd 185 p_itrq<5> 30 ide<7> 82 gnd 134 xwre_exwr 186 p_itrq<4> 31 ide<6> 83 vdd 135 eird 187 p_itrq<3> 32 gnd 84 vdd 136 eiwr 188 p_itrq<2> 33 vdd 85 gnd 137 vdd 189 p_itrq<1> 34 ide<5> 86 yde<1> 138 gnd 190 p_itrq<0> 35 ide<4> 87 yde<2> 139 eyrd 191 hold 36 ide<3> 88 yde<3> 140 eywr 192 holdack
63/66 ST18952 17.2 208 pin pqfp package dimensions table 17.1 208 pin pqfp package dimensions notes 1: lead finish to be 85 sn/15 pb solder plate. 37 ide<2> 89 yde<4> 141 clkout 193 gnd 38 gnd 90 yde<5> 142 incycle 194 vdd 39 vdd 91 yde<6> 143 mclk 195 gnd 40 ide<1> 92 vdd 144 ea_xae<0> 196 vdd 41 gnd 93 gnd 145 ea_xae<1> 197 erq 42 ide<0> 94 yde<7> 146 ea_xae<2> 198 idt_en 43 iwre 95 yde<8> 147 ea_xae<3> 199 mode 44 irde 96 vdd 148 ea_xae<4> 200 idle 45 ibse 97 gnd 149 ea_xae<5> 201 haltack 46 dmarq3_sck1 98 yde<9> 150 ea_xae<6> 202 clk_mode 47 dmarq2_srd1 99 yde<10> 151 vdd 203 ayebp 48 gnd 100 yde<11> 152 gnd 204 gnd 49 vdd 101 yde<12> 153 ea_xae<7> 205 vdd 50 dmarq1_sck0 102 yde<13> 154 ea_xae<8> 206 axebp 51 dmarq0_srd0 103 yde<14> 155 ea_xae<9> 207 aiebp_scan_en 52 dmack3_sfs1 104 yde<15> 156 ea_xae<10> 208 ird_wr ref. control dim. mm min nom max a 4.10 a1 0.25 a2 3.20 3.40 3.60 b 0.17 0.27 c 0.09 0.20 d 30.60 d1 28.00 d3 25.50 e 30.60 e1 28.00 e3 25.50 e 0.50 k 0d 3.5d 7d l 0.45 0.60 0.75 l1 1.30
64/66 ST18952 figure 17.1 208 pin pqfp package dimensions
65/66 ST18952 18 device id the identification code for the ST18952 is # m 52bc041, where m is a manufacturing revision number reserved by sgs-thomson. 19 ordering information for further information contact your local sgs-thomson sales office. 20 revision history this is revision 1 of this datasheet the differences between revision 1 and revision 0 are: clarification of sio0 and sio1 register addresses in osio registerso on page 36. refomatting of the presentation of the registers; the bit functions have be put into tables. addition of for pcsr and pcdr register information od950core registerso on page 14. addition of information for odmar: dma management registero on page 44. bit 31 bit 0 mask rev st18 family variant sgs-thomson manufacturers id 1) 1) defined as 1 in ieee 1149.1 standard. reserved 0 1 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 52bc041 device package ST18952x66s 208 pin plastic quad flat pack (pqfp)
index of registers 65/66 c cmr clock management register 44 d daic address/interrupt control register 24 dgc general control register 24 dmar dma management register 43 dms mask sensitivity control register 25 i icr interrupt control register 27 ier0/1 instruction memory control registers 20 imr interrupt mask/sensitivity register 29 intr interrupt vector register 43 ipr interrupt priority register 29 ispr interrupt stack pointer register 30 isr interrupt status register 30 ivo0-7 interrupt vector0-7 address registers 27 p pcdr port control direction 14 pcsr port control sensitivity 14 picr port/interrupt control register 42 s scor sio sequence control register 36 scr sio control register 36 ser sio enable register 38 sfr sio frequency register 38 srdr sio receive data register 40 ssr sio status register 39 stdr sio transmit data register 40 t tcr0-1 timer control register 31 tcvr0-1 timer current value register 33 tevr0-1 timer end value register 33 tsvr0-1 timer start value register 32 x xer0/1 x-memory space control registers 20 y yer0/1 y-memory space control registers 20 3
66/66 notes information furnished is believed to be accurate and reliable. however, sgs-th omson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-tho mson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-tho mson microelectronics products are not authorized for use as critical components in life support devices or systems without the express writt en approval of sgs-thomson microelectronics. ? 1997 sgs-thoms on microelectronics - all rights reserved. sgs-thoms on microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a.

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